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Interconnect Simulation & Innovation Engineer

About the Opportunity

We are establishing a brand-new division focused on pioneering a next-generation interface and interconnect methodology for the semiconductor test industry. As chip architectures evolve toward fine-pitch, chiplet, and high-frequency regimes, legacy test interfaces hit physical limitations. Our new division is tasked with building breakthrough interconnect solutions—from test sockets, test methods, contact pins and material to high-speed load boards.

 

As an Interconnect Simulation & Innovation Engineer, you will be a founding member of this technical team. You will leverage multi-physics simulation to analyze, optimize, and invent next-generation hardware that bridges semiconductor devices and test systems.

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Job Responsibilities

1. Multi-Physics Simulation & Analysis (Core Anchor + Domain Growth)

  • Signal Integrity (SI/PI): Model and simulate high-speed interconnect paths (S-parameters, crosstalk, eye diagrams, insertion/return loss) using 3D EM tools.

  • Mechanical FEA (Secondary/Collaborative): Evaluate pin contact forces, material deformation, mechanical fatigue, and structural integrity across cyclic test conditions.

  • Thermal Management (Secondary/Collaborative): Model heat dissipation, thermal expansion (CTE mismatch), and thermal interface behaviour under test conditions.

2. Next-Gen Interconnect Architecture & R&D

  • Concept development for novel contactors, pogo pins, flexible substrates, and high-bandwidth socket topologies.

  • Help define the physical design rules, stack-up parameters, and material selection (dielectrics, alloys, TIMs) for our new interconnect platform.

  • Co-invent hardware IP and document technical breakthroughs for patent filings.

3. Prototyping & Laboratory Validation

  • Work closely with PCB layout, mechanical design, and socket design division to translate simulation insights into physical prototypes.

  • Correlate simulation models against physical measurements using VNAs, TDRs, force frames, or thermal imaging equipment.

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Job Requirements

  • Bachelor’s, Master’s, or Ph.D. in Electronics/Electrical Engineering, Mechatronics, or Mechanical Engineering.

  • 3+ years in semiconductor test hardware, IC packaging, high-speed connector design, or high-speed PCB development.

  • Strong depth in at least ONE primary physics domain (Signal Integrity/EM OR Mechanical FEA OR Thermal CFD).

  • Proficiency in tools such as Ansys HFSS, CST Studio Suite, Cadence Sigrity, Keysight ADS, Ansys Mechanical, or SolidWorks Simulation.

  • An entrepreneurial, problem-solving mindset excited by a "0-to-1" greenfield environment.

 

Perks & Benefits

  • Competitive Salary, Performance Bonus and Yearly Increment

  • EPF, SOCSO & EIS Contributions

  • Medical/Hospitalization Coverage and Insurance

  • Dental and Optical

  • Comprehensive Internal & External Training Programs

  • Professional Growth & Career Advancement Opportunities

  • Onsite Gym Facilities

  • Comfortable Cafeteria/Pantry

  • Festive Gifts

  • Semi-Flexible Working Arrangement

  • Marriage, Maternity, Paternity Leaves

  • Free Parking

  • Accessible via public transport (MRT)

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Send your resume to:

JF Technology HR

Email: hr@jftech.com.my

Office: +603-6140 8668 (EXT. 280)

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