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Interconnect R&D, Strategy and Operations Manager

About the Opportunity

We are opening a brand-new division dedicated to deploying a next-generation interface and interconnect methodology to serve the semiconductor test industry. With rapid advancements in 2.5D/3D packaging, high-frequency SerDes, and thermal densities, traditional test board and socket architectures require a fundamental paradigm shift.

 

We are seeking a Manager or Senior Manager to lead this new business, operations and engineering division from inception. You will define the technology roadmap, build a high-performing team of simulation and hardware engineers, establish IP, and deliver next-generation interface solutions to our customers.

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Job Responsibilities

1. Division Leadership & Technology Strategy

  • Define and execute the strategic technology roadmap for our next-generation interconnect platform.

  • Translate industry trends (chiplets, fine-pitch sockets, HBM, high-speed ATE load boards) into commercial product features and engineering goals.

  • Manage division budget, R&D resource allocation, and key milestone deliverables.

2. Multi-Disciplinary Team Building & Governance

  • Recruit, mentor, and build an agile engineering team spanning Signal Integrity (SI/PI), Mechanical FEA, Thermal CFD, and PCB/Socket design.

  • Establish simulation-first design workflows to ensure high first-pass hardware success.

  • Balance complex engineering trade-offs between high-frequency signal performance, mechanical reliability, and thermal limits.

3. IP Generation & Commercial Deployment

  • Drive patent generation and protect proprietary interconnect concepts, pin geometries, and interface architectures.

  • Engage directly with key semiconductor customers and ecosystem partners to validate needs and co-develop customized interface platforms.

  • Partner with manufacturing and supplier networks to scale R&D concepts into commercial production.

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Job Requirements

  • Bachelor’s, Master’s, or Ph.D. in Electrical, Mechanical, Mechatronics, or Semiconductor Engineering.

  • 8+ years of technical leadership in high-speed interconnects, semiconductor ATE hardware, Test Sockets, IC packaging, or advanced connector R&D.

  • Broad understanding of Signal Integrity, mechanical design, thermal dynamics, and manufacturing processes for test hardware.

  • Proven ability to build engineering teams, manage product roadmaps, and drive technological innovation from concept to market.

 

Perks & Benefits

  • Competitive Salary, Performance Bonus and Yearly Increment

  • EPF, SOCSO & EIS Contributions

  • Medical/Hospitalization Coverage and Insurance

  • Dental and Optical

  • Comprehensive Internal & External Training Programs

  • Professional Growth & Career Advancement Opportunities

  • Onsite Gym Facilities

  • Comfortable Cafeteria/Pantry

  • Festive Gifts

  • Semi-Flexible Working Arrangement

  • Marriage, Maternity, Paternity Leaves

  • Free Parking

  • Accessible via public transport (MRT)
     

Send your resume to:

JF Technology HR

Email: hr@jftech.com.my

Office: +603-6140 8668 (EXT. 280)

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